Integrating and packaging all these technologies and components into a small standalone unit is another challenge. We also implemented a low-power RF trap drive, DC supplies to trap bias, FEA and C-field coil, and a microcontroller for the prototype clocks. This CMOS system was successfully used in one of the prototypes, demonstrating the future power reduction for M2TIC clocks when it is fully implemented. At the current stage, some additional discrete parts were used with the CMOS synthesizer chip to work in the current clock system. The first stage of the low-frequency PLL consumes only 1 mW while the entire multiplier part from the 20 MHz LO input to the 40.5 GHz clock signal consumes about 40 mW of power. The 40.5-GHz CMOS frequency synthesizer consists of a 900 MHz phase-locked loop (PLL) cascaded with a 40.5 GHz SSPLL to achieve the necessary large multiplication factor of 2025 from the designed 20 MHz input frequency. The SSPLL chip was fabricated using a 65-nm CMOS process. In the same clock development program, we developed a CMOS-based synthesizer scheme that bypasses part of the multiplication process by the sub-sampling phase-locked loop (SSPLL) technique 55, 56, 57. This conventional synthesizer uses frequency multipliers that are power hungry. Two of the prototypes used a commercial-of-the-shelf (COTS) synthesizer that consumes over 2.5 W of DC power. A synthesizer is needed to generate the 40.5 GHz signal that is phase locked to a quartz local oscillator (LO). At the same time, it makes the clock frequency source generation more challenging. This high microwave frequency provides a high quality factor and low magnetic sensitivity desired for a high-performance clock. ![]() The M2TIC prototypes could reach the \(10^, F=1 \rangle\) states. Here we demonstrate micro mercury trapped ion clock (M2TIC) prototypes integrated with novel micro-fabricated technologies to simultaneously achieve high performance and low SWaP. ![]() However, it has been challenging to break through the general trade-off trend between the clock stability performance and SWaP. As timing precision requirements increase, demands for lower SWaP (size, weight, and power) clocks rise. Modern communication and navigation systems are increasingly relying on atomic clocks.
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